1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a chip package structure and a manufacturing method thereof.
2. Description of Related Art
The production of IC devices can be mainly divided into three stages, including IC design, IC process and IC package.
During the IC process, a chip is fabricated by the steps of wafer process, IC formation and wafer sawing and so on. A wafer has an active surface, which generally means the surface comprising active devices. After the IC on the wafer is formed, the active surface of the wafer further includes a plurality of bonding pads so that the chip formed by wafer sawing can be externally electrically connected to a carrier through the bonding pads. The carrier may be a lead frame or a package substrate. The chip can be connected to the carrier by wire bonding or flip chip bonding, so that the bonding pads on the chip are electrically connected to the contact pads of the carrier, thereby forming a chip package structure.
FIG. 1 is a schematic cross-sectional view of a conventional chip package structure. The conventional chip package structure 100 includes a circuit substrate 110, a chip 120, a plurality of bonding wires 130, an encapsulant 140 and a plurality of solder balls 150. The circuit substrate 110 has a first surface 112, a second surface 114 and a through hole 116. The through hole connects the first surface 112 and the second surface 114. Furthermore, the chip 120 has an active surface 122 and a plurality of bonding pads 124, wherein the bonding pads 124 are disposed on the active surface 122, and the second surface 114 of the circuit substrate 110 is opposite to the active surface 122 of the chip 120. The through hole 116 exposes the bonding pads 124.
The bonding wires 130 respectively connect the bonding pads 124 and the first surface of the circuit substrate 110, and the bonding wires 130 pass through the through hole 116. The encapsulant 140 encapsulates a part of the active surface 122, the bonding wires 130 and a part of the first surface 112. The encapsulant 140 has a top surface 142, a bottom surface 144 and a side wall 146 on the first surface 112. The top surface 142 of the encapsulant 140 is away from the first surface 112, and the bottom surface 144 is in contact with a part of the first surface 112. Besides, the area of the bottom surface 144 is larger than the area of the top surface 142, so that a draft angle θ is formed between the perpendicular line of the side wall 146 and the first surface 112.
In the molding process, the shape of the encapsulant 140 is the same as the shape of the mold cavity of the mold, and the function of the draft angle θ is to facilitate the encapsulated chip package structure 100 to be smoothly removed from the mold. Therefore, different sizes of chip package structures 100 require different shapes of the molds, which greatly increases the manufacturing cost of the molds. In addition, overflow may sometimes occur during the molding process, resulting in contamination of the first surface 112 of the circuit substrate 110.